Design and FPGA implementation of power efficient turbo decoder for 4G LTE standards

The wireless communication has two significant blocks across transmitter and receivers are encoders and decoders. This work focuses on the design and implementation of turbo decoder in hardware description language (HDL) in verilog version. The turbo codes are very efficient in channel coding and are reaching the Shannon limit. The proposed design for turbo decoder uses the max-log algorithms instead of using max-log-MAP algorithm which computes on approximation. The design reduces the fixed number of iteration and performs the early termination which greatly reduces the power consumption utilized even after the decoding is completed. For early termination, the Sign Difference Ratio (SDR) is considered and across the hardware coding clock gating is introduced to avoid the unnecessary clock supply to achieve the power efficiency. The entire design has been implemented on vertex 4 and vertex 5 of Xilinx FPGAs. The power analysis is made and compared with recent existing technologies. © Research India Publications.