FPGA Implementation of Sorting Network for Median Filter Using pipelining processing

Digital Image Processing (DIP) is an ever expanding and dynamic area with vast applications reaching out into our day to day life. During the transmission of images over channels, images are often corrupted by impulse noise also known as salt and pepper noise due to faulty communications or noisy channels. The main problem in image processing is to reduce the effect of noise and present it with perceptible details. A standard signal processing requirement is to remove randomly occurring impulses without disturbing the edges. The theory of filtering gives optimal methods to remove these impulses. It is well known that linear filtering techniques fail when the noise is non-additive and are not effective in removing impulse noises. This led to the use of non-linear signal processing techniques. A class of widely used non-linear filters is median filters. Median filters are known for their capability to remove impulse noise as well as in preserving edges. Median filters commonly used in image processing applications are separable median filters, recursive median filters, weighted median filters, max-median filters and multistage median filters. Sorting networks are of major concern for real time hardware implementation of filters. Sorting is a computationally expensive operation as it consumes large area and power. Many researches have been done in reducing the complexity of the sorting networks.