Performance Evaluation of RingCounter using Gated Clock

Minimizing Power dissipation is one of the major concerns in the VLSI industry.Due the rapid growth in technology, there is atremendous reduction in the chip size. Minimum power consumption has become a priority.In this paper, we propose a low power designtechniquefor Ring counter using gated clock.In this paper, we demonstrate the working of ring counter using gated clock.The results areillustrated in Xilinx. The simulation results and the synthesis outputis shown.